EPAC: A RISC-V Accelerator from the European Processor Initiative

By Filippo Mantovani ¹, Fabio Banchelli ¹, Pablo Vizcaino ¹, Roger Ferrer ¹, Oscar Palomar ¹, ​​​​​​​Francesco Minervini ¹, ​​​​​​​Jesus Labarta ¹, ​​​​​​​Mauro Olivieri ¹, ​​​​​​​ Sebastiano Pomata ², ​​​​​​​Pedro Marcuello ², ​​​​​​​Jordi Cortina ², Alberto Moreno ², Josep Sans ², Roger Espasa ², Vassilis Papaefstathiou ³, Nikolaos Dimou ³, Georgios Ieronymakis ³, Antonis Psathakis ³, Michalis Giaourtas ³, Iasonas Mastorakis ³, Manolis Marazakis ³, Eric Guthmuller ⁴, Andrea Bocco ⁴, Jérôme Fereyre ⁴, César Fuguet ⁴, Mate Kovač ⁵, Mario Kovač ⁵, Luka Mrković ⁵, Josip Ramljak ⁵, Luca Bertaccini ⁶, Tim Fischer ⁶, Frank K. Gurkaynak ⁶, Paul Scheffler ⁶, Luca Benini ⁶, Bhavishya Goel ⁷, Madhavan Manivannan ⁷, Tiago Rocha ⁸, Nuno Neves ⁸, Jens Krüger ⁹,
¹ Barcelona Supercomputing Center, Spain
² Semidynamics, Spain
³ Foundation for Research and Technology– Hellas, Greece
⁴ Université Grenoble Alpes, CEA, LIST, France
⁵ University of Zagreb, Faculty of Electrical Engineering and Computing, Croatia
⁶ ETH Zürich, Switzerland
⁷ Chalmers University of Technology, Sweden
⁸ INESC-ID, Instituto Superior Técnico, Universidade de Lisboa Portuga
⁹ Fraunhofer ITWM, Germany

Abstract

This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe.

CCS Concepts

• Hardware →Integrated circuits; • Computer systems organization → Heterogeneous (hybrid) systems.

Keywords

RISC-V, European Processor Initiative, Vector Computing, Variable Precision, Stencil, Chip Tapeout, EPAC

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