Semiconductor IP Articles Archive - Page 3 of 228

Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation

By Jiale Liu, The University of Edinburgh

January 28, 2026

FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design

By Jiahao Zhang, University of California

January 27, 2026

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures

By Hansika Weerasena, University of Florida

January 26, 2026

CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device

By Ye Lin, Nanjing University

January 23, 2026

The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization

By Meng Li, Peking University

January 23, 2026

Pipeline Automation Framework for Reusable High-throughput Network Applications on FPGA

By Jean Bruant, OVHcloud

January 22, 2026

A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)

By eMemory & PUFsecurity

January 21, 2026

IMS: Intelligent Hardware Monitoring System for Secure SoCs

By Wadid Foudhaili, Universität zu Lübeck

January 19, 2026

Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs

By Mostafa Darvishi, Evolution Optiks Limited

January 14, 2026

Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications

By Vijay Pratap Sharma, Indian Institute of Technology Indore

January 14, 2026

PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference

By Nuntipat Narkthong, Northeastern University

January 13, 2026

Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

By Rui Xie, Rensselaer Polytechnic Institute

January 7, 2026

Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory

By Guan-Cheng Chen, National Cheng Kung University

January 6, 2026

ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update

By Zhe Su, University of Zurich and ETH Zurich

December 26, 2025

A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX

By Darja Nonaca, ETH Zurich

December 22, 2025

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor

By Mostafa Darvishi, ÉTS, Montreal

December 17, 2025

Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

By Juncheng Huo, Chinese Academy of Sciences

December 16, 2025

Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval

By Grant Bosworth, Rochester Institute of Technology

December 15, 2025

Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension

By Songqiao Cui, KU Leuven

December 10, 2025

ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes

By Dilli Babu Porlapothula, International Institute of Information Technology

December 9, 2025