Semiconductor IP Articles Archive - Page 3 of 231

GenAI-Driven Approach to RISC-V Supply Chain Exploration

By Nenad Petrovic, Technical University of Munich

May 25, 2026

HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip

By Pei-Huan Tsai, Columbia University

May 21, 2026

Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM

By Nicola Barcarolo, University of Trento

May 20, 2026

Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors

By Ruimin Shi, KTH Royal Institute of Technology

May 19, 2026

TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing

By Yavuz Selim Tozlu, North Carolina State University

May 18, 2026

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA

By Michelangelo Barocci, Politecnico di Torino

May 13, 2026

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core

By Pragun Jaswal, Indian Institute of Technology Mandi

May 13, 2026

ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits

By Lukas Sekanina, Brno University of Technology

May 12, 2026

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

By Johann Knechtel, New York University Abu Dhabi

May 12, 2026

Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling

By Yinrong Li, ETH Zurich

May 11, 2026

Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL

By Sajjad Ahmed, Barcelona Supercomputing Center (BSC)

May 6, 2026

EPAC: A RISC-V Accelerator from the European Processor Initiative

By European Processor Initiative

May 5, 2026

AceleradorSNN: A Neuromorphic Cognitive System Integrating Spiking Neural Networks and Dynamic Image Signal Processing on FPGA

By Daniel Gutierrez, Intigia

May 5, 2026

VitaLLM: A Versatile and Tiny Accelerator for Mixed-Precision LLM Inference on Edge Devices

By Zi-Wei Lin, National Yang Ming Chiao Tung University

May 4, 2026

SCENIC: Stream Computation-Enhanced SmartNIC

By Benjamin Ramhorst, ETH Zurich

April 29, 2026

Agentic AI-based Coverage Closure for Formal Verification

By Sivaram Pothireddypalli, Infineon

April 29, 2026

Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors

By Weiying Wang, University of Chinese Academy of Sciences

April 27, 2026

RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification

By Nick Andreasyan, Automotive Safety Lab

April 21, 2026

Emulation-based System-on-Chip Security Verification: Challenges and Opportunities

By Tanvir Rahman, University of Florida

April 20, 2026

A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting

By Fang-Chi Chang, National Yang Ming Chiao Tung University

April 15, 2026