TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link
March 3, 2026
Semiconductor IP Articles Archive - Page 2 of 228
AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance
February 27, 2026
LUTstructions: Self-loading FPGA-based Reconfigurable Instructions
February 25, 2026
CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
February 24, 2026
GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
February 23, 2026
Creating a Frequency Plan for a System using a PLL
February 18, 2026
RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
February 18, 2026
MING: An Automated CNN-to-Edge MLIR HLS framework
February 16, 2026
Fault Tolerant Design of IGZO-based Binary Search ADCs
February 13, 2026
A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
February 13, 2026
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
February 12, 2026
IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology
February 11, 2026
System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
February 10, 2026
CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
February 10, 2026
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
February 5, 2026
In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
February 4, 2026
QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
February 2, 2026
ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
February 2, 2026
COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
January 30, 2026
A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
January 28, 2026