Semiconductor IP Articles Archive - Page 2 of 232

Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency

By Chaoqun Liang, University of Bologna

September 1, 2026

Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems

By Hakam Atassi, University of Oxford

August 31, 2026

LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension

By Pingqing Zheng, University of Minnesota

August 28, 2026

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

By Po-Chuan Wang, Georgia Institute of Technology

August 25, 2026

Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework

By Chee Jin Teoh, Universiti Teknologi Malaysia

August 25, 2026

VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration

By Haoran Geng, University of Notre Dame

August 25, 2026

CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace

By Alexander Weiss, Accemic Technologies

August 24, 2026

A Resource-Efficient CNN-Based EEG Auditory Attention Decoding ASIC

By Qier Ma, Technische Universitat Dresden

August 21, 2026

Retention-Aware RISC-V ISA Extension and Memory Controller on FPGA for MLC NVM

By Mina Ibrahim, German University in Cairo (GUC)

August 17, 2026

Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference

By Rúben Teixeira, IObundle, Lda

August 14, 2026

HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA

By Christophe Clienti

August 13, 2026

Hybrid ASIC-FPAA Fabric for Performance Security Trade-off

By Ziyi Chen, Drexel University

August 12, 2026

A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs

By Mohammed Sajjad Jafri, University of Waterloo

August 11, 2026

A Low-Latency ASIC Architecture for Real-Time Line Segment Detection

By Amir Hossein Jalilvand, Iran University of Science and Technology

August 10, 2026

BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision

By Ang Li, Delft University of Technology

August 5, 2026

A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference

By Amirhossein Zarei, INRS-EMT

August 3, 2026

Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching

By Wiebren Wijnstra, University of Twente

July 30, 2026

SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow

By Andrija Nešković, Universität zu Lübeck

July 29, 2026

A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition

By Zhifan Song, Sorbonne University

July 28, 2026

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

By Benjamin Hubinet, CEA-Leti

July 27, 2026