Semiconductor IP Articles Archive - Page 2 of 229

A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core

By Pragun Jaswal, Indian Institute of Technology Mandi

May 13, 2026

ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits

By Lukas Sekanina, Brno University of Technology

May 12, 2026

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

By Johann Knechtel, New York University Abu Dhabi

May 12, 2026

Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling

By Yinrong Li, ETH Zurich

May 11, 2026

Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL

By Sajjad Ahmed, Barcelona Supercomputing Center (BSC)

May 6, 2026

EPAC: A RISC-V Accelerator from the European Processor Initiative

By European Processor Initiative

May 5, 2026

AceleradorSNN: A Neuromorphic Cognitive System Integrating Spiking Neural Networks and Dynamic Image Signal Processing on FPGA

By Daniel Gutierrez, Intigia

May 5, 2026

VitaLLM: A Versatile and Tiny Accelerator for Mixed-Precision LLM Inference on Edge Devices

By Zi-Wei Lin, National Yang Ming Chiao Tung University

May 4, 2026

SCENIC: Stream Computation-Enhanced SmartNIC

By Benjamin Ramhorst, ETH Zurich

April 29, 2026

Agentic AI-based Coverage Closure for Formal Verification

By Sivaram Pothireddypalli, Infineon

April 29, 2026

Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors

By Weiying Wang, University of Chinese Academy of Sciences

April 27, 2026

RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification

By Nick Andreasyan, Automotive Safety Lab

April 21, 2026

Emulation-based System-on-Chip Security Verification: Challenges and Opportunities

By Tanvir Rahman, University of Florida

April 20, 2026

A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting

By Fang-Chi Chang, National Yang Ming Chiao Tung University

April 15, 2026

SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation

By Zicheng He, University of California, Los Angeles

April 13, 2026

TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks

By Marco Bertuletti, ETH

April 8, 2026

Assertain: Automated Security Assertion Generation Using Large Language Models

By Shams Tarek, University of Florida, Gainesville

April 6, 2026

VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems

By Akram Ben Ahmed, National Institute of Advanced Industrial Sciences and Technology

April 3, 2026

A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators

By Luca Colagrande, ETH Zurich

April 1, 2026

Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification

By Antonino Armato, Robert Bosch

March 31, 2026