Agentic AI-based Coverage Closure for Formal Verification

By Sivaram Pothireddypalli ¹, Ashish Raman ², Deepak Narayan Gadde ³, Aman Kumar ^1
1 Infineon Technologies India Private Limited, India
² Dr. B R Ambedkar National Institute of Technology Jalandhar, India
³ Infineon Technologies Dresden AG & Co. KG, Germany

Abstract

Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines. This study presents an agentic AI-driven workflow that utilizes Large Language Model (LLM)-enabled Generative AI (GenAI) to automate coverage analysis for formal verification, identify coverage gaps, and generate the required formal properties. The framework accelerates verification efficiency by systematically addressing coverage holes. Benchmarking open-source and internal designs reveals a measurable increase in coverage metrics, with improvements correlated to the complexity of the design. Comparative analysis validates the effectiveness of this approach. These results highlight the potential of agentic AI-based techniques to improve formal verification productivity and support comprehensive coverage closure.

Index Terms — Agentic AI, LLM, Hardware Design, Formal Verification, Coverage

To read the full article, click here