Semiconductor IP Articles Archive - Page 9 of 232

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices

By Arya Parameshwara, PES University

November 11, 2025

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference

By Maximilian Kirschner, FZI Research Center for Information Technology

November 10, 2025

AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing

By Mohsen Ahmadzadeh, KU Leuven

November 6, 2025

FeNN-DMA: A RISC-V SoC for SNN acceleration

By Zainab Aizaz, University of Sussex

November 4, 2025

Multimodal Chip Physical Design Engineer Assistant

By Yun-Da Tsai, National Taiwan University

November 3, 2025

An AUTOSAR-Aligned Architectural Study of Vulnerabilities in Automotive SoC Software

By Srijita Basu, Chalmers University of Technology

November 3, 2025

Attack on a PUF-based Secure Binary Neural Network

By Bijeet Basak, International Institute of Information Technology

October 29, 2025

BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement

By Ke Xue, Nanjing University

October 28, 2025

FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics

By Philippe Flatresse, SOITEC

October 28, 2025

In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips

By Ismail Emir Yüksel, ETH Zürich

October 27, 2025

SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference

By Hengrui Zhang, Princeton University

October 23, 2025

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining

By Muhammad Hassan, Tallinn University of Technology

October 22, 2025

ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors

By Nuntipat Narkthong, Northeastern University

October 21, 2025

Practical Considerations of LDPC Decoder Design in Communications Systems

By Wasiela

October 15, 2025

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems

By Thomas Benz, ETH Zurich

October 15, 2025

A logically correct SoC design isn’t an optimized design

By Rick Bye, Arteris

October 15, 2025

AI in VLSI Physical Design: Opportunities and Challenges

By Japesh Kumar, Qualcomm

October 14, 2025

cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications

By Xi Wang, University of California

October 8, 2025

From Principles to Practice: A Systematic Study of LLM Serving on Multi-core NPUs

By Tianhao Zhu, Shanghai Jiao Tong University

October 8, 2025

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage

By Junius Pun, Nanyang Technological University

October 6, 2025