Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency By Abhishek BV, eInfochips (An Arrow Company) April 26, 2025
All-in-Memory Stochastic Computing using ReRAM By João Paulo C. de Lima, Dresden University of Technology April 24, 2025
How to Design Secure SoCs: Essential Security Features for Digital Designers By KiviCore April 15, 2025
A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans By Jonathan Cruz, Sandia National Laboratories April 10, 2025
Learning Cache Coherence Traffic for NoC Routing Design By Guochu Xiong, Nanyang Technological University April 9, 2025
Generative AI for Analog Integrated Circuit Design: Methodologies and Applications By Danial Noori Zadeh, McMaster University April 9, 2025
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction By Aritra Dasgupta, University of Florida April 9, 2025
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions By Vincenzo Petrolo, VLSI Lab, Politecnico di Torino, Italy April 8, 2025
A Time for Rebalancing Global Patent Strategies in the Semiconductor Market? By Greg Corcoran, Greg Corcoran IP April 7, 2025
Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs By Andy Nightingale, Arteris April 4, 2025
The pivotal role power management IP plays in chip design By Chris Morrison, Agile Analog April 2, 2025
Analyzing Modern NVIDIA GPU cores By Rodrigo Huerta, Universitat Politècnica de Catalunya March 31, 2025
RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware By Tomi Rantakari, ChipFlow March 28, 2025
Leveraging RISC-V as a Unified, Heterogeneous Platform for Next-Gen AI Chips By Akeana March 27, 2025