Highest performance IP for graphics, AI/ML
- PHY
- Samsung
- 10nm
- LPP
- Available on request
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster.
The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements.
Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Highest performance IP for graphics, AI/ML
The 224G SerDes PHY enables the emerging 1.6T and 800G networks for hyperscale data center and artificial intelligence (AI) infrastructures.
The 56G Long-Reach (LR) SerDes PHY provides exceptional performance with best-in-class power and area, making it ideal for machine learning (ML) and 5G infrastructure application
32G NRZ Multi-Protocol PHY
DDR4, DDR3 PHY and Controller
10G-KR, XFI, PCIe 3.1/2.0/1.0, XAUI, QSGMII, SGMII, Gigabit Ethernet
D-PHY physical layer
Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems
Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications
10Gbps Multi-Link and Multi-Protocol PHY IP
Designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express (PCIe) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, QSGMII
The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput.
Application-optimized, high-performance controller IP for PCIe
Controller IP for the MIPI I3C interface
CSI-2 transmitter controller for application processor
Audio data transport
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-low area and energy cost
Low-power, long-reach, multi-protocol PHY for PCIe 4.0
The first IP for PCIe 3.1 with L1 sub-states support