Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

224G-LR SerDes PHY

The 224G SerDes PHY enables the emerging 1.6T and 800G networks for hyperscale data center and artificial intelligence (AI) infrastructures.

PHY TSMC 3nm N3A Available on request View all specifications

Overview

Accelerate the Growth of Hyperscale Data Center

The ever-increasing bandwidth in high-performance computing (HPC) applications is driving the rapid growth of high-speed I/O capability. The Cadence 224G SerDes PHY enables the emerging 1.6T and 800G networks for hyperscale data center and artificial intelligence (AI) infrastructures. The IP incorporates industry-leading digital signal processing (DSP) SerDes technology to support LR, MR, and VSR at 1.25 to 225Gbps data rates.

Key features

  • Optimized Performance, Power and Area with Design Agility
  • Supports full-duplex 1.25 to 225Gbps data rates
  • Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
  • Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
  • Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects
  • Low power with configurability for different channel reaches
  • Beachfront-optimized floorplan allows north-south and east-west SoC edge placement
  • Comprehensive on-chip diagnostic features make system testing and debugging quick and easy

Block Diagram

224G-LR SerDes PHY block diagram

Benefits

High Performance

  • Best-in-class DSP provides superior data recovery for long-reach lossy and reflective channels

Flexibility

  • Supports different channel reaches with power configurability

Compliance to Evolving Industry Standards

  • Protocol compliance to evolving IEEE and OIF standards

Applications

  • Communications
  • Data Processing

What’s Included?

  • GDS II macros with abstract in LEF
  • Verilog post-layout netlist and Verilog models of I/O pads, and RTL for all PHY modules
  • Verilog models of I/O pads, and RTL for all PHY modules
  • STA scripts for use at chip or standalone PHY levels
  • Verilog testbench with memory model, configuration files, and sample tests

Silicon Options

Foundry Node Process Maturity
TSMC 3nm N3A Available on request

Specifications

Identity

Part Number
224G-LR SerDes PHY
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Single-Protocol PHY IP

What is 224G-LR SerDes PHY?

224G-LR SerDes PHY is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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