Vendor: Cadence Design Systems, Inc. Category: PCI Express

Controller for PCIe

Application-optimized, high-performance controller IP for PCIe

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Overview

The Cadence® Controller IP for PCI Express® (PCIe®) is architected to quickly and easily integrate into any SoC, and addresses a wide range of high-performance as well as low-power requirements for a broad spectrum of applications, including high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), supercomputing platforms, storage solutions, server applications, and mobile platforms. The controller area is optimized for each application to provide you with the best power and performance.

Key features

  • The Cadence Controller IP for PCIe is compliant with PCIe 6.0, 5.0, 4.0, 3.1, 2.1, 1.1 protocol versions and supports the latest ECNs including IDE/DOE so that applications can benefit from the latest updates to the specifications
  • The controller IP is available as root-port, end-point, or dual-mode to allow for versatile use cases, and multifurcation support allows applications to build configurations that can support configurations from 1x16 to 16x1 easily
  • The controller provides SR-IOV support with 256 functions and 4K payload size, scalable I/O virtualization with PASID is also available
  • Benchmarked at 95% of theoretical performance, superscalar design for high throughput and low latency at all data rates, applications have a choice of client interfaces for maximum performance

Block Diagram

Controller for PCIe block diagram

Benefits

  • Mature: Compliance-proven IP, with customer SoCs in volume production over many generations
  • Application Optimized: IP features optimized for key verticals like storage, automotive, enterprise, and AI/ML, configured to your specific needs with minimal gate count
  • Ease of Use: Fully verified pre-integrated IP delivery, with firmware and testbenches for rapid bring-up

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

What’s Included?

  • Clean, readable, synthesizable RTL Verilog files
  • Verification testbench example with integrated stimulus and monitors
  • Verification test-plan and reports
  • Register descriptions
  • Synthesis and STA scripts

Specifications

Identity

Part Number
Controller for PCIe
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about PCI Express IP core

Understanding PCIe 6.0 Power States: L0p vs L0s vs L1

PCIe 6.0 introduces a major shift in power-state strategy: the real battle is no longer between L0 and L1—it is between L0p, L0s, and L1.  In this blog, we explore how these states differ, why PCIe 6.0 changes the rules, and which one matters most moving forward.

Demystify Address Translation Services (ATS) in PCIe 6.0

Address Translation Services (ATS) is one of the toughest verification problems to solve as it is the fast lane for PCIe memory access, cutting delays by caching address translations directly on the device. It keeps software behavior consistent across both PCIe Devices and RC Integrated Endpoints, making performance gains simple to adopt.

Frequently asked questions about PCIe IP cores

What is Controller for PCIe?

Controller for PCIe is a PCI Express IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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