Vendor: Cadence Design Systems, Inc. Category: MIPI PHY

MIPI D-PHY

D-PHY physical layer

MIPI D-PHY TSMC 7nm N7+ Silicon Proven View all specifications

Overview

The Cadence IP for MIPI® D-PHYsm integrates a high-speed transmitter/receiver, low-power transmitter/receiver, and low-power contention detector that provide the full function of D-PHY. Our IP has an integrated PPI interface for ease-of-integration with MIPI CSI-2 and DSI controllers.

The Design IP for MIPI D-PHY provides lane flexibility with a compact and rectangular IP footprint, meeting usage models of modern SoCs. The pre-integrated CSI-2 and DSI solution ensures the interoperability and makes this PHY easy to integrate, shortening the product's time to market.

Key features

  • Multiple Configurations Possible. TX-only (with integrated PLL), RX-only, and combined TX and RX configurations
  • Complete Function for HS TX/RX, LP TX/RX, and LPCD with automatic termination control for high-speed and low-power modes
  • Integrated BIST Capable of producing and checking PRBS, CRPAT, and CJTPAT

Block Diagram

MIPI D-PHY block diagram

Benefits

  • Available as Pre-Integrated Solution with Controller: Cadence CSI-2 and DSI supported
  • Scalable, Modular Design: Compact and regular footprint
  • Supports Advanced FinFET Processes: 16nm, 12nm, and 7nm processes supported

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

What’s Included?

  • GDS II macros with abstract in LEF
  • Verilog post-layout netlist
  • STA scripts for use at chip or standalone PHY levels
  • Liberty timing model
  • SDF for back-annotated timing verification

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Silicon Proven

Specifications

Identity

Part Number
MIPI D-PHY
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Standards & Interfaces

MIPI PHY
MIPI D-PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about MIPI PHY IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about MIPI PHY IP

What is MIPI D-PHY?

MIPI D-PHY is a MIPI PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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