Vendor: Cadence Design Systems, Inc. Category: DDR

DDR4/3 PHY and Controller

DDR4, DDR3 PHY and Controller

Controller + PHY + 1 DDR4 TSMC 7nm N7+ Available on request View all specifications

Overview

Cadence DDR solutions, a family of high-speed on-chip interface IP, are leading the way for high-performance computing (HPC) systems and data center applications. The DDR PHY IP is engineered to quickly and easily integrate into any system on chip (SoC) and is verified with the DDR Controller IP as part of a complete memory subsystem solution. These IP are available as a product-optimized solution for specific applications, such as DDR4 and DDR3, with many configuration options to select desired features and integration aspects.

Key features

PHY

  • DDR4/3 training with write-leveling and data-eye training
  • Optional clock gating available for low-power control
  • Internal and external datapath loop-back modes
  • I/O pads with impedance calibration logic and data retention capability
  • Programmable per-bit (PVT compensated) deskew on read and write datapaths
  • RX and TX equalization for heavily loaded systems

Controller

  • Sideband and in-line SEC/DED ECC
  • Supports advanced RAS features including error scrubbing, parity, etc.
  • Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
  • Memory controller interface complies with DFI standards up to version 5.0
  • Priority per command on Arm® AMBA® 4 AXI, AMBA 3 AXI
  • Single and multi-port host interface options
  • QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
  • Silicon proven and shipping in volume

Block Diagram

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Benefits

  • Low Latency: For data-intensive applications
  • High Performance: Highest performance DDR5 at 12.8Gbps
  • Reliable: Maximum system margin with advanced clocking and I/O architectures

Applications

  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace

What’s Included?

  • GDSII macros with abstract in LEF
  • Verilog post-layout netlist
  • STA scripts for use at chip or standalone PHY levels
  • Liberty timing model
  • SDF for back-annotated timing verification

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Available on request

Specifications

Identity

Part Number
DDR4/3 PHY and Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
DDR4

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about DDR Interface IP

What is DDR4/3 PHY and Controller?

DDR4/3 PHY and Controller is a DDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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