Vendor: Cadence Design Systems, Inc. Category: DDR

DDR/LPDDR PHY and Controller

LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller

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Overview

Cadence DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput while balancing power consumption and minimizing area. The DDR/LPDDR PHY and Controller IP are developed and validated to reduce risk for the customer so that their SoC will work right the first time. Available as a product-optimized solution for specific applications such as DDR5/LPDDR5, DDR4/LPDDR4, DDR3/LPDDR3, and additional multiple protocol combinations.

Key features

PHY

  • DDR5/4/3 training with write-leveling and data-eye training
  • Optional clock gating available for low-power control
  • Internal and external datapath loop-back modes
  • I/O pads with impedance calibration logic and data retention capability
  • Programmable per-bit (PVT compensated) deskew on read and write datapaths
  • RX and TX equalization for heavily loaded systems

Controller

  • Sideband and in-line SEC/DED ECC
  • Supports advanced RAS features including error scrubbing, parity, etc.
  • Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
  • Memory controller interface complies with DFI standards up to version 5.0
  • Priority per command on Arm® AMBA® 4 AXI, AMBA 3 AXI
  • Single and multi-port host interface options
  • QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
  • Silicon proven and shipping in volume

Block Diagram

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Benefits

  • Multi-protocol Solution: DDR and LPDDR supported in a single IP
  • Highly Configurable: Application-specific parameters and floorplan optimization
  • Low Power and Area: Industry-leading PPA based on advanced architecture and implementation
  • Low Latency: For data-intensive applications
  • Reliable: Maximum system margin with advanced clocking and I/O architectures
  • Future proof: Cutting edge technology with the latest GDDR protocols and the highest data rates

Applications

  • Data Processing

What’s Included?

  • Clean, readable, synthesizeable Verilog RTL
  • Synthesis and STA scripts
  • Documentation—integration and user guide, release notes
  • Sample verification testbench with integrated BFM and monitors

Specifications

Identity

Part Number
DDR/LPDDR PHY and Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

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Frequently asked questions about DDR Interface IP

What is DDR/LPDDR PHY and Controller?

DDR/LPDDR PHY and Controller is a DDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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