Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

PHY for PCIe 3.1

The first IP for PCIe 3.1 with L1 sub-states support

PCIe Gen3 View all specifications

Overview

The Cadence IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols. ​

Key features

  • Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
  • Multi-protocol support for simultaneous independent links
  • Supports SRIS and internal SSC generation
  • Supports PCIe L1 sub-states
  • Automatic calibration of on-chip termination resistors
  • Supports internal and external clock sources with clock active detection
  • SCAN, BIST, and serial/parallel loopback functions

Block Diagram

PHY for PCIe 3.1 block diagram

Benefits

  • Multi-Protocol with Multi-Link Capability: Single-PHY macro offers optimum SoC configurability with the protocol mix and match
  • Optimized Performance, Power, and Area: Best fit for the application's required performance with small footprint
  • Comprehensive Test Feature Enables Rapid SoC Development: Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging

What’s Included?

  • PMA Hard Macro
  • PCS-BIST Soft Macro
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

Specifications

Identity

Part Number
PHY for PCIe 3.1
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen3

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about Single-Protocol PHY IP

What is PHY for PCIe 3.1?

PHY for PCIe 3.1 is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP