Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

112G-ULR PAM4 SerDes PHY

Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…

Compliant PHY TSMC 6nm +1 N6 +1 Available on request View all specifications

Overview

Accelerates AI and Hyperscale Data Center Applications

The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach performance, optimized power and area that is ideal for next-generation hyperscale data center, artificial intelligence (AI), optical, and 5G wireless applications. The SerDes PHY IP supports PAM4 and NRZ signaling and data rates from 1G to 112G with industry-leading digital signal process (DSP) technology incorporating maximum likelihood sequence detector (MLSD) to support up to a 45dB channel. It enables reliable high-speed data transfer over backplane, direct-attached cable (DAC), chip-to-chip, and chip-to-module channels to support LR, MR, and VSR use cases.

Key features

  • Supports full-duplex 1.25Gbps to 112.5Gbps data rates
  • Superior bit error rate (BER) performance across high-loss and reflective channels
  • Compliant with IEEE 802.3ck and OIF standard electrical specifications
  • Supports flexible SoC floorplan and IP placement and provides package substrate guideline/reference designs
  • Available in multiple advanced-process nodes, including 3nm, 4nm, 5nm, 6nm, and 7nm
  • Up to 800G Ethernet subsystem delivery with Cadence High-Speed Ethernet Controllers

Applications

  • Communications
  • Data Processing

What’s Included?

  • GDS II macros with abstract in LEF
  • Verilog post-layout netlist
  • f STA scripts for use at chip or standalone PHY levels
  • Liberty timing model
  • SDF for back-annotated timing verification

Silicon Options

Foundry Node Process Maturity
TSMC 6nm N6 Available on request
TSMC 7nm N7 Available on request

Specifications

Identity

Part Number
112G-ULR PAM4 SerDes PHY
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Application
Data center , Edge AI
Controller / PHY
PHY

Standards & Interfaces

Compliance Status
Compliant

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about Single-Protocol PHY IP

What is 112G-ULR PAM4 SerDes PHY?

112G-ULR PAM4 SerDes PHY is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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