Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

56G-LR Pam4 SerDes PHY

The 56G Long-Reach (LR) SerDes PHY provides exceptional performance with best-in-class power and area, making it ideal for machine learning (ML) and 5G infrastructure application

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PHY TSMC 7nm N7+ Silicon Proven View all specifications

Overview

Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems.

The 56G-LR SerDes PHY IP supports PAM4 and NRZ signaling and data rates from 1Gbps to 56Gbps. This silicon-proven IP incorporates industry-leading analog-to-digital converter (ADC), clock-data-recovery (CDR) and digital signal process (DSP) technology that enables the support of greater than 45dB channel.

Key features

  • Supports Ethernet, FC, CPRI, and eCPRI protocols
  • Compliant to IEEE 802.3ck and OIF standard electrical specifications
  • Supports 56Gbps PAM4 and 28G, 10G, and sub-10Gbps NRZ data rates
  • Unique firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
  • Continuous calibration and adaption provide robust performance across process, voltage, and temperature
  • Supports industrial temperature range -40°C – 125°C

Benefits

  • High Flexibility: Multi-rate support provides backward compatibility with legacy equipment operating at lower speeds
  • Robust Performance: ADC/DSP-based receiver architecture provides superior data recovery for lossy and noisy channels
  • Ease of Use: Fully autonomous startup and adaptation, SNR monitoring, as well as integrated BIST capable of producing and checking PRBS

Applications

  • Communications
  • Data Processing

What’s Included?

  • GDS II macros with abstract in LEF
  • Verilog post-layout netlist
  • STA scripts for use at chip or standalone PHY levels
  • Liberty timing model
  • SDF for back-annotated timing verification

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Silicon Proven

Specifications

Identity

Part Number
56G-LR Pam4 SerDes PHY
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

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Frequently asked questions about Single-Protocol PHY IP

What is 56G-LR Pam4 SerDes PHY?

56G-LR Pam4 SerDes PHY is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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