Vendor: Cadence Design Systems, Inc. Category: CXL

Controller for CXL

Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications

Contact Provider Request Datasheet

Overview

The Cadence Controller IP for CXL addresses a wide range of high-bandwidth and low-latency requirements for a broad spectrum of applications, including high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), storage solutions, accelerators, and memory expanders.

Key features

  • The Cadence Controller IP for CXL provides the logic required to integrate a root-port (RP), end-point (EP), or dual-mode (DM) controller into any system on chip (SoC), and supports CXL 3.1, CXL 2.0 and CXL 1.1
  • Designed for lowest latency at the highest bandwidth possible and with a rich set of client interfaces available, the Cadence Controller IP for CXL allows superior flexibility for all three device types in the CXL specification
  • The Cadence Controller IP for CXL has been robustly verified with lead OEM partners in pre-silicon, and the Cadence subsystem test chips for PCIe and CXL include a CXL controller

Block Diagram

Controller for CXL block diagram

Benefits

  • High Performance, Low Latency: Benchmarked at 95% of theoretical performance, superscalar design for high throughput and low latency
  • Application Optimized: IP features optimized for key applications like storage, managed memories, and AI/ML accelerators, configured to your specific needs with minimal gate count
  • Ease of Use: Fully verified pre-integrated IP delivery, with firmware and testbenches for rapid bring-up

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

What’s Included?

  • Clean, readable, synthesizable RTL Verilog files
  • Verification testbench example with integrated stimulus and monitors
  • Comprehensive user guide
  • Register descriptions
  • Synthesis and STA scripts

Specifications

Identity

Part Number
Controller for CXL
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about CXL IP core

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity.

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder.

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.

An Overview of CXL Mode Alternate Protocol Negotiation

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers. One of the most common alternate protocols is the Compute Express Link (CXL), which provides a high-bandwidth, low-latency communication with cache coherency, memory sharing, and I/O support. CXL includes three sub-protocols: CXL.io, CXL.cache, and CXL.mem.

Evolution of CXL PBR Switch in the CXL Fabric

As technology continues to advance, so do the ways we connect and manage and access memory in our computing systems, there is a Port-Based Routing (PBR) in a CXL fabric is a key innovation introduced in CXL 3.0 and 3.1 that enables flexible, scalable, and efficient connected and communication across a computing environment, that revolutionized how CXL switches operate within a CXL fabric

Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems

As technology continues to advance, so do the ways we connect and manage memory and devices in our computing systems. The latest version of Compute Express Link (CXL) 3.1 introduces a feature known as extended metadata. This feature brings significant improvements to how memory transactions are handled, leading to better performance and efficiency. Let's break down what extended metadata is, why it's important, and how it could make a difference in your systems.

Frequently asked questions about CXL IP cores

What is Controller for CXL?

Controller for CXL is a CXL IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP