Vendor: Cadence Design Systems, Inc. Category: Multi-Protocol PHY

PHY for PCIe 6.0 and CXL

Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems

Overview

Cadence PHY IP for PCI Express® (PCIe®) 6.0 is a high-performance NRZ/PAM4 SerDes designed specifically for infrastructure and data center applications. The SerDes’s ultra-long-reach equalization and robust clock-data recovery capabilities allow it to achieve unparalleled performance and reliability. In addition, the SerDes IP features low data path latency and low power consumption, making it ideal for deployment in time-sensitive applications in high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), data communications, networking, and storage systems.

Key features

  • Architecture optimized for HPC, AI/ML, storage, and networking
  • Ultra-long reach, low latency, and low power
  • Advanced DSP delivers unmatched performance and reliability
  • Comprehensive real-time diagnostic, monitor, and test features
  • Bifurcation support for x1, x2, x4, x8, and x16 lanes

Block Diagram

PHY for PCIe 6.0 and CXL block diagram

Benefits

  • High Performance: DSP-based equalization and clock-data-recovery (CDR) offer unmatched channel loss handling performance and reliability
  • Flexibility: Highly configurable PHY with support for PCIe, CXL, and common electrical standards
  • Lowest Risk: Brings Cadence’s expertise in PAM4 and PCIe together in the implementation of this emerging standard
  • Ease of use: Fully verified, pre-integrated IP delivery, with package and signal integrity support and firmware for faster bring-up

Applications

  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace

What’s Included?

  • Integration Views: Verilog behavioral model, GDSII, CDL, and power models
  • Synthesizable RTL
  • DFT-Verilog netlists with SS/FF, CTL, and BSDL
  • Reference Verilog testbenches used for generating SoC-level VCD ATE test patterns for PHY
  • IBIS-AMI kit

Specifications

Identity

Part Number
PHY for PCIe 6.0 and CXL
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Multi-Protocol PHY IP core

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard

Modern compute systems have evolved beyond reliance on a single dominant interface. Today, they're increasingly defined by their ability to support multiple high-speed protocols concurrently—including PCIe, Ethernet, and others. This shift toward multi-protocol capability is fundamentally reshaping how we architect intelligent edge AI systems, especially as inferencing workloads grow more distributed, data-intensive, and latency-sensitive.

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.

Frequently asked questions about Multi-Protocol PHY IP cores

What is PHY for PCIe 6.0 and CXL?

PHY for PCIe 6.0 and CXL is a Multi-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP