DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a TX PHY

The DP/eDP Combo TX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a. It consists of configurable numbers of (1, 2, or 4) main link channels and one AUX channel. It supports main link speed rates from RBR  (1.62Gbps) to HBR3 (8.1Gbps), and 1Mbps Manchester II coding for the AUX channel.

The IP targets the growing broad adoption of digital display technology within the PC and CE industries. It consolidates internal and external connection methods to reduce device complexity, supports necessary features for key-cross industry applications, and offers scalable performance, enabling next-generation displays with larger color depths, refresh rates, and resolutions.

• Compliant to DP v1.4a and eDP v1.4a
• Consists of four main link channels, one AUX channel, and one clock multiplier PLL
• Supports 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.7Gbps (HBR), 5.4 Gbps (HBR2), and 8.1 Gbps (HBR3) for DP
• Supports both wire bond and flip chip
• Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
• Supports programmable output swing, termination, and pre-emphasis
• Supports 1, 2, or 4 lanes at 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, 5.4 Gbps, and 8.1 Gbps for eDP