1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…
- Multi-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…
PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5…
XEC is a high performance 1000M/100M/10M Ethernet Controller IP.
The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
The Nuclei Universal Serial Bus (USB) Controller is compliant with the USB 2.0 Specification to support high-speed,full-speed or …
CMOS camera.
Serial Audio Interface/Inter-IC Sound
The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configur…
The Improved Inter Integrated Circuit (I3C) is part of a group of communication protocols defined by the MIPI Alliance.
I2C (Inter-Integrated Circuit) bus Interface serves as an interface between the microcontroller and the serial I2C bus.
Controller Area Network with Flexible Data rate
The XKAN module is a communication controller implementing the CAN protocol specification version 2.0 part A, B and CAN with Flex…
General Purpose Input/Output controller
The Nuclei LGPIO (Logic general-purpose I/Os) describes the operation of the Logic General Purpose Input/Output Controller(LGPIO).
Full duplex asynchronous communications
The USART (Universal Synchronous Asynchronous Receiver Transmitter) offers a flexible means of full-duplex data exchange with ext…
The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
SWI3S (SoundWire I3S Interface) Manager Controller
Implements & supports MIPI SoundWire-I3S Specification
SLI UHS-II PHY Analog IP consists of a mixed-signal SERDES supporting both Full Duplex and Half Duplex modes.
Ethernet Switch VLAN 5x100M
Ethernet Switch/Router L2/L3/MPLS 12x10G
This L3 Ethernet Switch/Router IP core is built around a shared buffer memory architecture providing wire-speed switching and rou…
Ethernet Switch/Router Enterprise 9x10G + 2x25G
This is a L2 switch and an IP/MPLS router with ACL engines.
Ethernet Switch/Router Datacenter ToR 32x100G
This L2/L3 Ethernet Switching/Routing Core offers full wire-speed on all 32 ports, with up to 100 Gbit of bandwidth per port.
The USB device core is compliant with revision 1.1.