A integrated hardware and software solution that includes a TSN-capable Ethernet switch, a DMA engine, an IEEE 802.1 AS Time Sync…
- Protocol Bridge
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
A integrated hardware and software solution that includes a TSN-capable Ethernet switch, a DMA engine, an IEEE 802.1 AS Time Sync…
Size optimized, Silicon agnostic, Silicon Proven Ethernet PCS IP core for High Speed Ethernet applications The 200G/400G Ethernet…
10M/100M/1G/10G/25G Unmanaged Ethernet Switch
Silicon-Agnostic, Compact and flexible Ethernet Switch IPs Unmanaged Ethernet Switch IP cores are a family of Ethernet switching …
The DisplayPort 1.4 Transmitter PHY is for transmitting high-definition video and audio, making it an ideal choice for a wide ran…
Verification IP for CAN XL, FD and CAN 2.0
A comprehensive VIP solution portfolio for CAN XL, CAN FD and CAN 2.0 used by SoC and IP designers to ensure comprehensive verifi…
The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD.
The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stac…
The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard.
The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.
The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol.
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.
The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
MIPI D-PHY/LVDS Combo Transmitter IP
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer…
HDCP 2 on HDMI / DisplayPort Embedded Security Module Firmware (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …