Vendor: Synopsys, Inc. Category: Bus Fabric

Verification IP for AMBA AXI

Synopsys Verification IP (VIP) for Arm® AMBA® AXI™ provides a comprehensive set of protocol, methodology, verification and produc…

Verification IP View all specifications

Overview

Synopsys Verification IP (VIP) for Arm® AMBA® AXI™ provides a comprehensive set of protocol, methodology, verification and productivity features. Users are able to achieve rapid verification convergence on their AMBA AXI5, AXI-J/K, AXI4, AXI3, and AXI4-Lite based designs. 

Key features

  • Complete protocol support for AXI5, AXI-J/K, AXI4, AXI4-Lite, AXI3
  • Programmable number of Managers, Subordinates, and Port Monitors
  • Interconnect model
  • System Monitor
  • Port & System Level Sequencers
  • Sequence Library with port & System Level Sequences
  • Port level protocol checks for all interfaces
  • System-level checks for protocol and data integrity
  • Debug port for transaction tracking on waveforms
  • Built-in Functional Coverage Model
  • Protocol-aware debugging using Protocol Analyzer
  • Ability to control delays for valid and ready signals with respect to reference events
  • Ability to control signal values during idle periods

Block Diagram

Verification IP for AMBA AXI block diagram

Specifications

Identity

Part Number
Verification IP for AMBA AXI
Vendor
Synopsys, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

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Frequently asked questions about On-Chip Bus IP cores

What is Verification IP for AMBA AXI?

Verification IP for AMBA AXI is a Bus Fabric IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Bus Fabric?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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