Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Multi-Protocol PHY

1.25 Gbps-12.5 Gbps HSS for Supporting Multiple Protocols

The 1.25 Gbps to 12.5 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.

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Overview

The 1.25 Gbps to 12.5 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols. The PHY has 1-lane, 2-lane, and 4-lane versions for flexible applications. Additionally, HSS supports wide range datarates and multiple parallel data width. HSS also includes 3-tap programmable TX FFE, CTLE, and VGAs to maintain signal integrity across complex PCB environments. Multiple debug methods such as embedded eye monitor, BIST test, and boundary scan are provided to facilitate bug locating.

Key features

  • Operates over a wide range of data rates, including 1.25 Gbps, 2.5 Gbps, 3.125 Gbps, 5 Gbps, 6.25 Gbps, 8 Gbps, 10 Gbps, and 12.5 Gbps
  • Supports multiple protocols, each with its own dedicated PCS
  • Supports independent control of power state and data rate per lane
  • Provides comprehensive power-down control to optimize power modes
  • Supports configurable TX pre-emphasis and post-emphasis control
  • Supports integrated spread-spectrum generation with spread depth of up to 5000 ppm
  • Offers Built-in Self-Test (BIST) features for production, enabling at-speed testing on any digital tester
  • Includes embedded PRBS generator and PRBS checker to facilitate debugging
  • Supports wire-bond and flip-chip packaging technologies

Block Diagram

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Specifications

Identity

Part Number
1.25 Gbps-12.5 Gbps SerDes
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

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Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 1.25 Gbps-12.5 Gbps HSS for Supporting Multiple Protocols?

1.25 Gbps-12.5 Gbps HSS for Supporting Multiple Protocols is a Multi-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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