What is HDMI 2.0 TX PHY?
HDMI 2.0 TX PHY is a HDMI IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
HDMI
HDMI 2.0 TX PHY
HDMI TX PHY is the physical layer of a single-link HDMI transmitter interface.
Overview
HDMI TX PHY is the physical layer of a single-link HDMI transmitter interface. The HDMI TX PHY comprises three data lanes and one clock lane to perform the serialization and transmission of video/audio data and control information. The PHY can support maximum data rates 6Gbps/lane to satisfy HDMI 2.0 protocol. The PHY is suitable for 30b, 60b, or 120b input data transfers.
Key features
- Compatible with HDMI 2.0/1.4 TX PHY operation
- Supports up to 1080p at 120 Hz and 4K x 2K at 60 Hz HDTV display resolutions
- Supports 3-D video formats
- Supports deep color modes: 30, 36, and 48 bits
- Supports link controller interface with 30 bits, 60 bits, or 120 bits data access
- 50% duty-cycle output clock
- I2C interface for configuration
- Supports RX sensing and Hot Plug Detect (HPD)
- Source termination impedance is auto-calibrated
- Built-in Self-Test (BIST) is integrated inside
- Support TMDS clock range from 40MHz to 600MHz
Block Diagram
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Specifications
Identity
Part Number
HDMI 2.0 TX PHY
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY
Standards & Interfaces
Video Standard
HDMI
Files
Note: some files may require an NDA depending on provider policy.
Provider
Frequently asked questions about HDMI IP cores
How should engineers evaluate this HDMI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HDMI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.