VBO TX PHY

The VX1 Transmitter AFE receives 10-bit parallel data per lane from the digital core. This data is latched inside the VX1 AFE and then serialized by the serializer with the least significant bit (LSB) transmitted first. After serialization, the serial bit stream is sent to the pre-driver and driver. The driver converts incoming digital signals to analog signals and transfers them to the receiver chip. The VX1 Transmitter uses a half-rate clock system and multiplexes even and odd data using the adjustable PLL output clock.

• 16 or 8 differential data lanes
  • TX0 to Tx15 for 16-lane version
  • TX0 to Tx7 for 8-lane version
• Each lane supports 1.4 Gb/s to 4.0 Gb/s data rates (140–400 MHz word clock)
• Each lane can individually be enabled
• Each lane has its own analog driver, serializer, and sync block for communication to and from the VX1 MAC
• Each lane driver supports pre-emphasis
• Provides a built-in deserializer for loopback test and debug of data signals as well as pre-emphasis signals (both even and odd)
• Includes the following two communication signals: LOCKN and HTPDN
• Includes one common PLL, which supports spread spectrum modulation
• The low frequency part of each lane is scanable. The spread spectrum modulator and serializers (high-speed part) can be tested using the integrated de-serializer for date and pre-emphasis signals