DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY
The DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
Overview
The DP/eDP Combo RX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a. It consists of configurable numbers of (1, 2, or 4) main link channels and one AUX channel. It supports the main link speed rates from RBR(1.62Gbps) to HBR3(8.1Gbps) and 1Mbps Manchester II coding for the AUX channel.
It consolidates internal and external connection methods to reduce device complexity, supports necessary features for key cross-industry applications, and offers scalable performance, enabling next-generation displays with Larger color depths, refresh rates, and resolutions.
Key features
- Compliant to DP v1.4a and eDP v1.4a
- Consists of four main link channels, one AUX channel, and one common lane
- Supports 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.7 Gbps (HBR), 5.4 Gbps (HBR2), and 8.1 Gbps (HBR3) for DP
- Supports 1, 2, or 4 lanes at 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, 5.4 Gbps and 8.1 Gbps for eDP
- Supports Advanced Link Power Mode (ALPM)
- Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
- Adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
- Built-in on chip eye opening monitor (EOM)
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Displayport IP core
VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
Hexagon Semi’s HX77 AR Display Processor Achieves Ultra-Low Power Consumption with VeriSilicon’s Nano IP Portfolio
VeriSilicon Enhanced ISP8200-FS Series IP Achieves ASIL B Functional Safety Certification
VeriSilicon’s NPU IP VIP9000NanoOi-FS has achieved ISO 26262 ASIL B certification
VeriSilicon and Google Jointly Launch Open-Source Coral NPU IP
Frequently asked questions about DisplayPort IP cores
What is DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY?
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a RX PHY is a Displayport IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this Displayport?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.