USB 3.0 and PCIe 2.0 Combo PHY
The USB 3.0 SuperSpeed and PCI Express Combo PHY is a programmable IP compatible with the PHY Interface for the PCI Express Archi…
Overview
The USB 3.0 SuperSpeed and PCI Express Combo PHY is a programmable IP compatible with the PHY Interface for the PCI Express Architecture and USB 3.0 SuperSpeed Architecture specifications. The PHY supports the USB 3.0 SuperSpeed (5 Gbps) and PCI Express Gen1 (2.5 Gbps) and Gen2 (5.0 Gbps).
Key features
- Fully compatible with:
- USB 3.0 SuperSpeed: Universal Serial Bus 3.0 Specification, Revision 1.0
- PCI Express: PCI Express Base Specification, Revision 2.0
- Supports all USB 3.0 and PCIe 2.0 power management modes
- Supports PCIe L1 PM substates (L1.1 and L1.2) with CLKREQ#
- Spread spectrum clock (SSC) and data scrambling to minimize EMI
- Supports 16-bit 250 MHz and 32-bit 125 MHz PIPE interfaces for USB 3.0/PCIe Gen2
- Supports 16-bit 125 MHz and 32-bit 62.5 MHz PIPE interfaces for PCIe Gen1
- Supports a wide range of reference clocks: 25/50/60/100 MHz
- Multiple loopback and compliance test modes
- Built-in BIST pattern generator and checker with programmable modes for stand-alone tests
- On-chip Eye Opening Monitor (EOM) to measure the eye diagram at the RX side
- -3.5 dB/-6 dB de-emphasis at the TX side and programmable CTLE equalization at the RX side
- Supports programmable transmit swing:
- 8b /10b encoding and decoding implemented in hardware
- Supports LFPS generation and detection in USB 3.0 mode and beacon in PCIe mode
- IEEE standards 1149.1 and 1149.6 (JTAG) boundary scan for internal visibility and control
- APB and I2C interfaces to access the internal registers for different applications
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Multi-Protocol PHY IP cores
What is USB 3.0 and PCIe 2.0 Combo PHY?
USB 3.0 and PCIe 2.0 Combo PHY is a Multi-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this Multi-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.