Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: HDMI

HDMI 2.0 RX PHY

HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface.

PHY HDMI View all specifications

Overview

HDMI RX PHY is the physical layer of a single-port HDMI transmitter interface. The HDMI RX PHY comprises three data lanes and one clock lane to perform the serialization and transmission of video/audio data and control information. The PHY can support a maximum data rate of 6 Gbps/lane to satisfy HDMI 2.0 protocol. The PHY supports input data transfers of 30, 60, or 120 bits. 

Key features

  • Compatible with HDMI 2.0/1.4 RX PHY operation
  • Supports deep Color modes: 24, 30, and 36 bits
  • Includes an audio clock regeneration block
  • Production test and debug capabilities
  • Supports TMDS clock range from 25 MHz to 340 MHz
  • Supports TMDS character rate from 250 MHz to 600 MHz

Block Diagram

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Specifications

Identity

Part Number
HDMI 2.0 RX PHY
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Controller / PHY
PHY

Standards & Interfaces

Video Standard
HDMI

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about HDMI IP core

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Frequently asked questions about HDMI IP cores

What is HDMI 2.0 RX PHY?

HDMI 2.0 RX PHY is a HDMI IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this HDMI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HDMI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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