eUSB2 PHY

The embedded USB 2.0 (eUSB2) PHY is a high-speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. It provides a High/Full/Low-Speed USB analog front-end with a built-in 8-bit/16-bit parallel interface. Optimized for portable applications, the PHY  features low power dissipation in active and/or standby state, and a small area for low cost. The eUSB2 PHY supports both native mode and repeater mode. In native mode, the eUSB2 PHY supports board-level chip-to-chip communication. In repeater mode, the eUSB2 PHY supports standard USB 2.0 communication with discrete USB 2.0 PHY through a separate eUSB 2 repeater component.

• Compliant with the UTMI Specification Revision 1.05
• Compliant with the UTMI+ Specification Revision 1.0 Level 3
• Compliant with the eUSB 2.0 Specification Revision 1.2
• Not compatible with the physical layer defined by USB 2.0
• Not compatible with standard USB 2.0 connectors defined by USB 2.0 and its derivatives
• Fully integrates eUSB 2.0 eDP/eDM
• Supports 480 Mbps “High Speed”, 12 Mbps “Full Speed”, and 1.5 Mbpss “Low Speed”
  • High-Speed: Low voltage differential signaling
  • Low-Speed/Full-Speed: Single-ended digital low-voltage signaling
• Supports 60 MHz/8-bit interface and 30 MHz/16-bit interface
• Supports on-chip reference clock source
• Supports multiple reference clock frequencies: 12 MHz, 19.2 MHz, 20 MHz, 24 MHz, 38.4 MHz, 40 MHz, 50 MHz, etc.
• Integrates 40 Ω ± 20% termination and 4-10 kΩ pull-down resistor