UCIe Controller (CHI Protocol + Adapter)

The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers. The UCIe Protocol Layer is located between SoC logics and UCIe D2D Adapter Layer, handles the UCIe Protocol Layer functions. SoC logics communicate with UCIe Protocol Layer via the CHI Issue G interface. The Adapter Layer coordinates with the Protocol Layer and the Physical Layer to ensure successful data transfer across the UCIe Link. The Adapter Layer is responsible for coordinating higher-level link state machine, managing the link bring-up process, and exchanging parameters related to protocol options with the remote link partner. The UCIe Controller supports Streaming Protocol.

• Supports CHI Issue G Protocol Layer
• Supports C2C Packetization Layer
• Supports latency-optimized 256B flit format with optional bytes for Streaming Protocol
• Supports flit generation and extraction
• Supports clock domain crossings between the CHI clock and UCIe clock
• Compliant with the UCIe Specification 1.1
• Supports 32B for FDI and RDI data width
• Supports 8/16/32 bits for FDI and RDI CFG width
• Low latency for flit transfer in UCIe Controller
• Supports the APB4 interface with a 32-bit address and 32-bit data bus for local register access