CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
By Yuecheng Wang, Jonathan Woodruff, Alfredo Mazzinghi, Peter Rugg, Samuel W. Stark, Alexandre Joannou, Robert N. M. Watson, Simon W. Moore
University of Cambridge, United Kingdom
Abstract
We propose CHERI-D, an architectural extension to CHERI that supports efficient temporal memory safety. Efficient memory safety is an increasing priority for programming languages, operating systems, and hardware designs, and CHERI is a leading hardware/software system that provides native spatial safety and a foundation for temporal memory safety. Due to CHERI lacking intrinsic architectural support for temporal memory safety, the state-of-the-art CHERI temporal safety solution, Cornucopia Reloaded, is a software-based solution that provides use-after-reallocation (UAR) protections instead of the stronger use-after-free (UAF) mitigation, and suffers performance overhead due to delayed reallocation and revocation. CHERI-D associates object identification (ID) metadata with capability pointers to provide temporal integrity of allocations. CHERI spatial safety allows CHERI-D to store object IDs safely inline with allocation data, potentially within unused fragmentation. Evaluated in simulation and in hardware, CHERI-D significantly reduces the revocation overhead of Cornucopia Reloaded while allowing it to support strict use-after-free mitigation.
To read the full article, click here
Related Semiconductor IP
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
- AXI4 Memory Controller IP Core
- AXI-Lite I2C Controller Core
- LVDS Transceiver IP core
Related Articles
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains