AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing

By Shirui Zhao ^∗, Nimish Shah ^∗, Wannes Meert ^†, and Marian Verhelst ^∗
∗ MICAS-ESAT, KU Leuven
^† DTAI, KU Leuven

Abstract

Probabilistic graphical models (PMs) are popular to empower machine learning with the ability of reasoning and decision-making. To perform approximate inference in PMs, sampling-based Markov Chain Monte Carlo (MCMC) algorithms are commonly employed. Unfortunately, MCMC is compute intensive and hard to run in parallel, resulting in inefficient execution on modern CPU/GPU platforms. This paper proposes AIA, an Approximate Inference Accelerator designed to empower decision-making and reasoning at the edge. AIA consists of a RISC-V host, and a 2D mesh of 16 customized RISC-V cores optimized to efficiently support PM inference, each featuring (i) a novel non-normalized Knuth-Yao sampler and interpolation unit; and (ii) core-to-core direct data access via the register file, which provides solutions for compute-intensive operations. To fully exploit the parallel potential of Markov Chain Monte Carlo (MCMC) algorithms, a customized compiler chain has been developed for effective spatial mapping and scheduling on the chip. AIA can generate 1277 MSample/s at 0.9V and 20 GSamples/s/W at 0.7V which is up to 2× faster and 1.45x more energy efficient compared to the previous state-of-the-art Markov Random Field (MRF) accelerator. We further map Bayesian Networks benchmark onto AIA to show the flexibility of our design.

Index Terms: Probabilistic graphical models, Bayesian in ference, Approximate inference, MCMC, Knuth-Yao sampling, RISC-V

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