CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems
By Enrico Zelioli 1, Christopher Reinwardt 1, Nils Wistoff 1, Robert Balas 1, Alessandro Ottaviano 3, Luca Benini 1,2, Angelo Garofalo 1,2
1 Integrated Systems Laboratory, ETH Zurich
2 Department of Electrical, Electronic, and Information Engineering, University of Bologna
3 Tenstorrent
Abstract
This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implements the rv64gch ISA and features advanced support for real-time execution, including TLB partitioning and locking for predictable address translation, a dynamically reconfigurable scratchpad mode in the L1 caches for deterministic memory access, and low-latency interrupt handling via an enhanced interrupt controller combined with hardware-assisted context stacking. With real-time features enabled, CVA6-RT achieves an interrupt latency of 12 cycles, comparable to that of simpler Arm Cortex-M microcontrollers, and 10x lower than the baseline CVA6 core.
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