ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training

By Haihang Xia ¹, Xinyu Zhao ¹, Xuecheng Wang ¹, John Goodenough ¹, Charith Abhayaratne ¹, Panagiotis A. Panagiotou  ¹, Chunyi Song ^2,3,4, and Tiantai Deng ^5
1 School of Electrical and Electronic Engineering, The University of Sheffield, U.K.
² Donghai Laboratory, Zhoushan 316021, China
³ Engineering Research Center of Oceanic Sensing Technology and Equipment, Ministry of Education, Zhoushan 316021, China
⁴ State Key Laboratory of Ocean Sensing and Ocean College, Zhejiang University, Zhoushan 316021, China.
⁵ Donghai Laboratory, Zhoushan 316021, China

Abstract

Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications. However, the large number of synaptic connections in SNNs leads to intensive weight-update computation by on-chip learning algorithms during training, resulting in substantial hardware resource utilization and energy consumption. Among existing SNN learning algorithms, spike-timing-dependent plasticity (STDP) is one of the most extensively studied and widely adopted, serving as a fundamental learning component in SNNs. To address the hardware and energy overheads associated with SNN training, this paper presents intrinsic-timing power-of-two STDP (ITP-STDP) and its corresponding prototype learning engine hardware architecture. The proposed design is evaluated through a dedicated mean-field synaptic drift model for dynamical analysis and further validated across SNN networks of different scales and datasets. It is further implemented on both ASIC and FPGA platforms and compared with state-of-the-art approaches, including the original STDP and more complex STDP variants. The results demonstrate superior energy efficiency, higher operating speed, and substantially lower hardware resource utilization, as the proposed design eliminates most of the computational overhead of STDP through both algorithmic and hardware-level optimizations. On the FPGA platform, the proposed design improves energy efficiency by 4.5x to 219.8x over the compared designs. On the ASIC platform, the proposed design achieves a 4.8x to 22.01x speedup while consuming only 1.2% to 3.3% of the area required by prior works.

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