The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.
- SPI / QSPI XSPI
- Silicon Proven
- AHB
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.
AXI 5-Master Component Low-Latency SRAM Controller
The AXI 5-Master component SRAM Controller provides 5 AXI 64-bit Master components with low-wait-state access to a single interna…
HDLC frame to APB bridge , is cable of receive and transmit of HDLC frame .
The USB Host, as defined by the OHCI specification, is a hardware controller designed to manage communication between a host syst…
High-speed data transfer rates of up to 20 Gbps, doubling the bandwidth of USB 3.1 for faster performance and improved connectivity.
CPU-less TLS1.3 Offload IP core for FPGA Acceleration
TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no…
Extreme-Radix Switching for AI Scale-Up and Scale-Out Systems
Fully compliant with USB 3.2 specification version 1.1, xHCI Specification Revision 1.2, and Pipe Interface 6.1.1 with Message Bus Interface for USB3.2 Architecture
Production-grade PCIe® 6.x Controller IP — FPGA-validated validated for low-latency throughput, robust compliance, and easy FPGA/ASIC integration.
USB3.1 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…
JESD204B/204C IP with PHY and MAC layer
With sophisticated architecture and technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high perfo…
SATA/SAS 3.0 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture.
With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…
With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
High-speed LVDS (Low-Voltage Differential Signaling) transceiver
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint.
100G bps Full TCP & UDP Offload Engine
Government Network Equipment, Financial institutions in high frequency trading applications, Servers in data centers and data exc…
Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…