Interface Connectivity IP Cores

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.

• Protocol Bridge

The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…

• Bus Fabric
• Silicon Proven
• Now
• AHB

The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.

• SPI / QSPI XSPI
• Silicon Proven
• AHB

The AXI 5-Master component SRAM Controller provides 5 AXI 64-bit Master components with low-wait-state access to a single interna…

• Bus Fabric

HDLC frame to APB bridge , is cable of receive and transmit of HDLC frame .

• Protocol Bridge

The USB Host, as defined by the OHCI specification, is a hardware controller designed to manage communication between a host syst…

• USB

High-speed data transfer rates of up to 20 Gbps, doubling the bandwidth of USB 3.1 for faster performance and improved connectivity.

• USB4

TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no…

• Ethernet

The USB3.2 Verification IP provides an effective & efficient way to verify the components connected with USB3.2 interface of an I…

• Verification IP

With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…

• Single-Protocol PHY

With sophisticated architecture and technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high perfo…

• JESD204

With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …

• Single-Protocol PHY

RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture.

• RapidIO

With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…

• Single-Protocol PHY

With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…

• Multi-Protocol PHY

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• Multi-Protocol PHY

This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.

• MIPI C-PHY

This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint.

• Single-Protocol PHY

Government Network Equipment, Financial institutions in high frequency trading applications, Servers in data centers and data exc…

• Ethernet

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• PHY
• TSMC
• 28nm
• HPC
• Available on request