The DB1881AHB IP Core interfaces a Camera CMOS Image Sensor to Frame Buffer Memory via the AMBA AHB Interconnect.
- MIPI
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The DB1881AHB IP Core interfaces a Camera CMOS Image Sensor to Frame Buffer Memory via the AMBA AHB Interconnect.
The DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL…
The DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC …
SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave …
SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfer…
I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
The DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus.
The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AX…
I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) …
I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration…
I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP desig…
FlexGen Smart Network-on-Chip (NoC) IP
AI-enhanced automation for smarter SoC and chiplet designs.
PSI5 IP Core Controller for Peripheral Sensor Interface 5 Communication
The DPSI5 is a hardware implementation of a controller for the Peripheral Sensor Interface (PSI5) protocol.
The CXL Verification VIP provides an effective & efficient way to verify the components interfacing with CXL Switch interface of …
The UART /USART Verification IP provides an effective & efficient way to verify the components interfacing with UART/USART interf…
Automotive Ethernet Verification IP
The Automotive Ethernet Verification IP provides an effective & efficient way to verify the components interfacing with the 2.5G,…
With growing demand for flash memory in automotive, IoT, and consumer applications, the Host Controller IP for xSPI offers up to …
Proven PHY IP for USB3.1 with supporting multi-protocol feature
Most advanced PHY and controller IP for HPC, AI/ML, data communications, networking, and storage systems
Proven solution featuring host and peripheral