USB3.1 transceiver IP with PMA and PCS layer

With sophisticated architecture and advanced technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources. Data rate for Gen 1 physical layer is 5Gbps, and data rate for Gen 2 physical layer is 10Gbps.

• Data rate for Gen 1 physical layer is 5Gbps
• Data rate for Gen 2 physical layer is 10Gbps
• 4 Channel per Quad
• Shared high performance LC tank PLL
• Digitally-control-impedance termination resistors
• PLL Frequency Lock detection
• Configurable TX output differential voltage swing
• Built-in TX De-Emphasis
• RX Built-in CTLE and Decision Feedback Equalization
• Support IEEE 1149.1 and 1149.6(AC JTAG) boundary scan
• Built-in self-test(BIST) features for production
• Multiple Loop Back, BIST, and Analog DC Testing
• PRBS (PRBS-7, PRBS-15, PRBS-23, PRBS-31) generator and checker
• Low Power Consumption
• Supports Flip-Chip package

• GDSII&CDL Netlist
• Verilog Model
• LEF Layout Abstract(.LEF)
• Liberty Timing Models(.lib)
• Verify Results
• Specification
• Datasheet
• IntegrationGuideline
• Evaluation Plan
• Leading support for package design, SI&PI modeling and production test development