Vendor: KNiulink Semiconductor Ltd. Category: Single-Protocol PHY

PCIE 6.0/5.0/4.0/3.0/2.0

With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…

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Overview

With sophisticated architecture and advanced technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high performance application. PCS layer and PMA layer include RX, TX and a common lane. The interfaces between users and IP are PIPE interface. All the control and configuration bits of the SerDes PHY IP are assigned in register map at PCS side and can be accessed through JTAG interface and register access port.

Key features

  • Support PCI Expression Gen5 & Gen4 & Gen3 & Gen2 & Gen1
  • Configurable differential voltage swing
  • Embedded low jitter LC PLL with fixed bandwidth and output frequency
  • PLL Frequency Lock detection
  • Support termination resistance tuning
  • IEEE P1149.6-2003/P1149.1-2001(ACJTAG)
  • Support 32 Gbps PCIe Gen5, 16 Gbps PCIe Gen4, 8 Gbps PCIe Gen3, 5 Gbps PCIe Gen2 and 2.5 Gbps PCIe Gen1 Test mode
  • Support PCIe Beacon signaling
  • Advanced, built-in diagnostics including on-chip digital RX eye scope
  • Internal/external loopback
  • 8b/10b and 128b/130b encoding and decoding
  • Elastic Buffer
  • JTAG test port
  • Flip-Chip package supported

Block Diagram

PCIE 6.0/5.0/4.0/3.0/2.0 block diagram

What’s Included?

  • GDSII&CDL Netlist
  • Verilog Model
  • LEF Layout Abstract(.LEF)
  • Liberty Timing Models(.lib)
  • Verify Results
  • Specification
  • Datasheet
  • Integration Guideline
  • Evaluation Plan
  • Leading support for package design, SI&PI modeling and production test development

Specifications

Identity

Part Number
PCIE 6.0/5.0/4.0/3.0/2.0
Vendor
KNiulink Semiconductor Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact KNiulink Semiconductor Ltd.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is PCIE 6.0/5.0/4.0/3.0/2.0?

PCIE 6.0/5.0/4.0/3.0/2.0 is a Single-Protocol PHY IP core from KNiulink Semiconductor Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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