PCIe Gen 6 Phy
- Multi-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
PCIe Gen 6 Phy
A 2Gbps LVDS Tranceiver in TSMC 28nm This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power …
A 2Gbps SLVS Tranceiver in TSMC 28nm This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs…
2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
A 2Gbps differential transceiver.
Expanded Serial Peripheral Interface (xSPI) Slave Controller
The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited…
Expanded Serial Peripheral Interface (xSPI)Master Controller
The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use …
Universal Chiplet Interconnect Express(UCIe) VIP
The UCIe VIP , a solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of y…
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-C…
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-C…
DDR5 Serial Presence Detect (SPD) Hub Interface
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temper…
MIPI CSI -2 TRANSMITTER IP -V3
MIPI CSI-2 (Camera Serial Interface) Transmitter IP defines an interface between a peripheral device (camera) and host processor …
MIPI CSI-2 V3 RECEIVER INTERFACE IP
The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (applicatio…
MIPI-I3C Slave (SDR) RTL Design IP
MIPI I3C slave Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalabilit…
MIPI-I3C Master (SDR) RTL Design IP
MIPI I3C master Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalabili…
MIPI I3C Basic Slave Controller
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication.
MIPI I3C Basic Master Controller
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication.
The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and mai…
Low Pin Count (LPC) controller verification IP
The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance.
The vendor provides configurable CPRI TX/RX verification IP.
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB Lite bus …