Vendor: KNiulink Semiconductor Ltd. Category: JESD204

JESD204B/204C IP with PHY and MAC layer

With sophisticated architecture and technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high perfo…

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Overview

With sophisticated architecture and advanced technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high performance application. It is fully compatible with JESD204B/204C specification, and supports link rate up to 25Gbps per lane. Take JESD204B TX IP as an example, which assembles the parallel data from the ADCs into frames and uses 8b/10b encoding, as well as optional scrambling, to form serial output data. For the MAC side, it has the transport layer, which handles packing the data into the JESD204B frames. Besides, the data link layer is responsible for the low level functions of passing data across the link. For the PMA side, it has four lanes and a common block.

Key features

  • X4/X8 Lane Mode, support up to 25Gbps (per lane)
  • Shared common PLL based architecture
  • Digitally-control-impedance termination resistors and On-chip resistance calibration
  • Configurable TX output differential voltage swing
  • Built-in TX De-Emphasis
  • RX Built-in Decision Feedback Equalization
  • PLL Frequency Lock detection
  • Support BIST, and Analog DC Testing
  • Fully Compatible with JESD204B/204C standard release
  • Supports Subclasses 0, 1
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Deterministic latency support
  • PRBS (PRBS-7/PRBS-15/PRBS-23/PRBS-31) generator and checker
  • Support data polarity inversion
  • 8b/10b and 64b/66b encoding
  • Optional Scrambling/De-Scrambling
  • Register control through APB interface

Block Diagram

JESD204B/204C block diagram

What’s Included?

  • GDSII&CDL Netlist
  • Verilog Model
  • LEF Layout Abstract(.LEF)
  • Liberty Timing Models(.lib)
  • Verify Results
  • Specification
  • Datasheet
  • Integration Guideline
  • Evaluation Plan
  • Leading support for package design, SI&PI modeling and production test development

Specifications

Identity

Part Number
JESD204B/204C
Vendor
KNiulink Semiconductor Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact KNiulink Semiconductor Ltd.

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204B/204C IP with PHY and MAC layer?

JESD204B/204C IP with PHY and MAC layer is a JESD204 IP core from KNiulink Semiconductor Ltd. listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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