MIPI C/D PHY
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
Overview
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. This IP supports data rate up to 2.5Gbps.
Key features
- Compatible with MIPI D-PHY v1.2/CSI-2 protocol
- Up to 4-lane 2.5Gbps/ lane
- Support 2-Lane/4-Lane Application
- Support HS mode (80Mbps to 2.5Gbps per lane) and LP mode (up to 10Mbps)
- Support low power mode
- Integrated control interface logic to support PHY Protocol Interface (PPI)
- Supports up to four virtual channel
- Support apb interface
- Support DFT and BIST
- Support 2048x1536@60Hz
- CSI-2 ECC Detection and CRC Generation
- Special packets for frame start, frame end, line start and line end information
- Description for the type, pixel depth and format of the application specific payload data
- Programmable parameters
Block Diagram
What’s Included?
- GDSII&CDL Netlist
- Verilog Model
- LEF Layout Abstract(.LEF)
- Liberty Timing Models(.lib)
- Verify Results
- Specification
- Datasheet
- Integration Guideline
- Evaluation Plan
- Leading support for package design, SI&PI modeling and production test development
Specifications
Identity
Standards & Interfaces
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about MIPI PHY IP core
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Frequently asked questions about MIPI PHY IP
What is MIPI C/D PHY?
MIPI C/D PHY is a MIPI PHY IP core from KNiulink Semiconductor Ltd. listed on Semi IP Hub.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.