Vendor: Silvaco, Inc. Category: SPI / QSPI XSPI

AHB-Lite Slave to SPI Master

The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.

Overview

The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol is implemented on the SPI bus.

The AHB-Lite to SPI Bridge has two AHB-Lite Slave component interfaces; one for access to the control/status registers (Register Interface), and another for access to the external SPI device (External Interface). The Bridge also has a SPI interface that operates exclusively as a SPI Master component device.

Key features

  • 32 bit serial transmit & receive
  • AHB Configuration Register Interface
  • AHB Interface for accessing external SPI device
  • Dual-bit or Single-bit mode operation
  • Asynchronous SCLK operation
  • 32 word Transmit FIFO
  • 16 word Receive FIFO
  • Interrupt control
  • LSB mode
  • Support for all SPI modes (CPOL, CPHA)
  • Up to 4 Slave components under Master component control

Block Diagram

AHB-Lite Slave to SPI Master block diagram

What’s Included?

  • Verilog Source
  •  Complete Test Environment
  •  AHB Bus Functional Model

Specifications

Identity

Part Number
70147
Vendor
Silvaco, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Silvaco, Inc.
HQ: United States

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Frequently asked questions about SPI / QSPI / xSPI IP cores

What is AHB-Lite Slave to SPI Master?

AHB-Lite Slave to SPI Master is a SPI / QSPI XSPI IP core from Silvaco, Inc. listed on Semi IP Hub.

How should engineers evaluate this SPI / QSPI XSPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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