Vendor: KNiulink Semiconductor Ltd. Category: Multi-Protocol PHY

Combo SerDes

With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…

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Overview

With sophisticated architecture and advanced technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources; it can support a wide variety of serial data transmission protocols with link rate up to 25/28/32Gbps.

Key features

  • 4 Channels per Quad
  • Data rate up to 25/28/32Gbps
  • Shared Quad LC-PLL for high performance
  • Independent Ring-PLL of each channel for clock flexibility
  • Support the following protocols: CEI-25G/28G/PCIE4.0/JESD204C/ USB3.1/10G-KR/SATA3/DP1.4
  • Digitally-control-impedance termination resistors
  • Configurable TX output differential voltage swing
  • Built-in TX De-Emphasis
  • RX Built-in CTLE and Decision Feedback Equalization
  • Multiple Loop Back, BIST, and Analog DC Testing
  • Support RX Built-in Eye Opening Monitor
  • Support Boundary Scan Interface for Serial link, compliant with IEEE 1149.6-2003/ 1149.1-2001
  • BIST (PRBS-7, PRBS-15, PRBS-23, PRBS-31, fixed-pattern) generator and checker
  • Low Power Consumption
  • Supports Flip-Chip package

Block Diagram

Combo SerDes block diagram

What’s Included?

  • GDSII&CDL Netlist
  • Verilog Model
  • LEF Layout Abstract(.LEF)
  • Liberty Timing Models(.lib)
  • Verify Results
  • Specification
  • Datasheet
  • Integration Guideline
  • Evaluation Plan
  • Leading support for package design, SI&PI modeling and production test development

Specifications

Identity

Part Number
Combo SerDes
Vendor
KNiulink Semiconductor Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact KNiulink Semiconductor Ltd.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is Combo SerDes?

Combo SerDes is a Multi-Protocol PHY IP core from KNiulink Semiconductor Ltd. listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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