Vendor: Certus Semiconductor Category: Multi-Protocol PHY

2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm

A 2Gbps differential transceiver.

Overview

A 2Gbps differential transceiver. Dynamically select between LVDS or SLVS with selectable on-die termination and pre-emphasis.

AD_SLVS_LVDS is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die termination and pre-emphasis, this I/O is flexible enough for any system. To compliment this I/O, the vendor also offers a accompanying silicon-proven ESD and GPIO pad library in TSMC 12/16nm. This I/O provides 2kV HBM protection but can be extended up to 8kV upon request.

Operating Conditions

Parameter Value
VDDIO 1.8V
Core VDD 0.8V
Tj -40C to 125C

 

Key features

  • Dynamically select between SLVS or LVDS
  • 2Gpbs transmit and receive modes
  • Available 100  on-die termination
  • Selectable pre-emphasis for high speeds at heavier loads
  • 2kV+ HBM protection, +500V CDM protection
  • Input and output enable/disable

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 16nm 16nm 160 nm —

Specifications

Identity

Part Number
AD_LVDS_SLVS
Vendor
Certus Semiconductor
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: United States

Learn more about Multi-Protocol PHY IP core

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This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.

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Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.

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Frequently asked questions about Multi-Protocol PHY IP cores

What is 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm?

2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm is a Multi-Protocol PHY IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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