MIPI SPMI Target Controller

The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits(PMIC) voltage regulation systems.

• Compliance as per MIPI Alliance Specifiction version 2.0
• Support SCLK frequency Low Speed - 32kHz to 15MHz
• Support SCLK frequency High Speed - 32kHz to 26MHz
• Supported command sequences are
1. Register 0 Write
2. Register Write
3. Register Read
4. Extended Register Write
5. Extended Register Read
6. Extended Register Write Long
7. Extended Register Read Long
8. Reset
9. Sleep
10. Wakeup
11. Shutdown
• Support Bus Arbitration
• Support Parity Check
• Support of generate parity
• Register Access using command sequence

• Verilog Source code.
• User Guide.
• IP Integration Guide.
• Simulation script.
• Synthesis script.
• Encrypted UVM Verification Testbench Environment.
• Basic Testsuite.