This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
- MIPI D-PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself …
The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.
I3C Dual/Secondary Controller IP v1.2
The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specificati…
I3C Dual/Secondary Controller IP
The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specificati…
The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.
The CAN-XL Bus Controller Core performs serial communication as per CAN 2.0, CAN-FD & CAN-XL Specifications.
The CAN-SEC Acceleration Engine Core implements the CAN-XL Protocol (CiA 610-1), CAN-XL Addon Part 1-Simple/Extercontent Indicati…
CAN FD LIGHT BUS CONTROLLER IP
The Controller Area Network – Flexible Data-Light (CAN-FD Light) Controller IP implements the CAN FD-Light (CIA 604-1) protocol.
The SPMI Host and Device IP (Configurable Controller Cores) implements MIPI SPMI2.0 protocols.
The MIPI C/D-PHY combo IP is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for …
The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and receptio…
LVDS Tunneling Protocol and Interface (LTPI) IP
LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 Specification to facilitate the tunneling …
GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs.
The 10GBASE-R PHY Intel® FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or…
100 G Ethernet MAC & PCS IP Core
The 100 Gbps Ethernet IP solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Et…
MIPI DSI2
MIPI CSI-2