MIPI SPMI HOST CONTROLLER
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-C…
Overview
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits(PMIC) voltage regulation systems.
Key features
- Compliance as per MIPI Alliance Specifiction version 2.0
- Support SCLK frequency Low Speed - 32kHz to 15MHz
- Support SCLK frequency High Speed - 32kHz to 26MHz
- Supported command sequences are
- Register 0 Write
- Register Write
- Register Read
- Extended Register Write
- Extended Register Read
- Extended Register Write Long
- Extended Register Read Long
- Reset
- Sleep
- Wakeup
- Shutdown
- Master write
- Master read
- Transfer Bus Ownership
- Support Bus Arbitration
- Support Parity Check
- Support of generate parity
- Register Access using command sequence
- SCLK Handover
Block Diagram
What’s Included?
- Verilog Source code.
- User Guide.
- IP Integration Guide.
- Simulation script.
- Synthesis script.
- Encrypted UVM Verification Testbench Environment.
- Basic Testsuite.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about MIPI IP cores
What is MIPI SPMI HOST CONTROLLER?
MIPI SPMI HOST CONTROLLER is a MIPI IP core from MAXVY Technologies Pvt Ltd listed on Semi IP Hub.
How should engineers evaluate this MIPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.