USB1.1 build-in clock PHY, HLMC 40LP
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
- USB 1.1
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
USB1.1 build-in clock PHY, HLMC 40LP
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB1.1 build-in clock PHY, SamSung LFR6LP
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB1.1 build-in clock PHY, SamSung LF6S
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB1.1 build-in clock PHY, SamSung LF6
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB1.1 build-in clock PHY, TSMC 110g
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB2.0 build-in clock PHY, HLMC 55LP, type-C
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB2.0 build-in clock PHY, HLMC 40LP, type-C
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB2.0 build-in clock PHY, TSMC 110g
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB3.0 build-in clock PHY, HLMC 40LP, type-C
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
USB3.0 build-in clock PHY, TSMC 110g
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function.
eUSB2 v1.1 Dual-Role, repeater/native mode PHY, SamSung 3LPE, 1.2V, N/S orientation
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
eUSB2 v1.2 Dual-Role, repeater/native mode PHY, SamSung SF3P, 1.0V, N/S orientation
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
eUSB2 v1.1 Dual-Role, repeater/native mode PHY, TSMC N5, 1.2V, N/S orientation
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
USB2.0 Dual-Role PHY, TSMC 55EF
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
The PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations.
The DP and eDP TX/RX PHY IP provides a compact, low-power solution for high-speed external display interfaces.
DisplayPort 1.2a TX PHY targeting 28nm Artix-7
DisplayPort 1.2a compatible AMD/Xilinx hardware specific Hardware proven on AMD/Xilinx 28nm FPGA fabric Fabric: 28nm Artix-7 Tran…
PCIe 5.0 PHY, SS SF5 x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …