LVDS receiver - TowerJazz 0.13um
LVDS receiver
- Tower
- 130nm
- SL
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
LVDS receiver - TowerJazz 0.13um
LVDS receiver
LVDS reference - TowerJazz 0.13um
LVDS reference
Brite provides USB2.0 OTG PHY which is a mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (So…
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
High-Speed LVDS (SERDES) Transceiver
The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applicatio…
The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and h…
The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and…
10Base-T Interface - requires no PHY
Full support for 10Base-T, full- or half-duplex
LVDS serdes 4:28 channel decompression RX 8-150Mhz
FPD-LINK 24-bit color, 8-150Mhz Receiver LVDS serdes 4:28 channel decompression RX 56-1050 Mbs x4 V-Trans 's FPD Link Receiver Ma…
LVDS serdes 28:4 channel compression TX 20-170Mhz
LVDS serdes 28:4 channel compression TX 140-1190 Mbs x4 FPD-LINK Transmitter 24-bit color 20-170Mhz This FPD Link Transmitter Mac…
Serial ATA (SATA) PHY Transceiver IP
SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS.
PCI Express PIPE PHY Transceiver
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling.
Integrates MAC IP to a broad range of PHY and SerDes IP
Long reach SerDes for Automotive Sensor and Display Applications
Long Reach SerDes for Automotive Sensor and Display Applications
The embedded USB 2.0 (eUSB2) PHY is a high-speed System-on-Chip (SoC) integrated transceiver IP in process that implements the In…
The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…