TaraCom announces GPON SerDes IP PHY in 90 nm process
TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC design.
Vendor:
TaraCom Integrated Products, Inc.
Category:
Single-Protocol PHY
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
Overview
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY. TRC3002CSA uses double data rate (DDR) transmission for send and receive side. Same Device can operate as a Serial ATA Gen I at 1.5Gb/s and at 3Gb/s Serial ATA Gen 2. Spread Spectrum Clock (SSC) is used to minimize EMI and increase the quality of received signal. It can transmit and receive through a 40-inch cable.
Each transmit section of the TRC3002CSA contains a low-jitter clock synthesizer, an 8-bit or 10-bit parallel to serial converter with built in 8b/10b encoder, and differential high speed Interface output. Its receive section contains an input limiting amplifier with on-chip terminations, a clock/data recovery PLL, a Comma detector, a serial to parallel converter with built-in 8b/10b decoder. OOB circuitry complies with SATA Gen 1 and Gen 2 Standards, featuring COMRESET/COMINIT, and COMWAKE commands and detection.
It has a built-in serial Near and Far End Loopback. SLUMBER and PARTIAL Power Down feature can minimize the power consumption of device. TRC3002CSA is fabricated with TSMC’s advanced 0.13uM CMOS logic process, and is also available as standard product (TRC3002SSA).
Each transmit section of the TRC3002CSA contains a low-jitter clock synthesizer, an 8-bit or 10-bit parallel to serial converter with built in 8b/10b encoder, and differential high speed Interface output. Its receive section contains an input limiting amplifier with on-chip terminations, a clock/data recovery PLL, a Comma detector, a serial to parallel converter with built-in 8b/10b decoder. OOB circuitry complies with SATA Gen 1 and Gen 2 Standards, featuring COMRESET/COMINIT, and COMWAKE commands and detection.
It has a built-in serial Near and Far End Loopback. SLUMBER and PARTIAL Power Down feature can minimize the power consumption of device. TRC3002CSA is fabricated with TSMC’s advanced 0.13uM CMOS logic process, and is also available as standard product (TRC3002SSA).
Key features
- Serial ATA fully compliant to Gen 1 and Gen 2 SATA PHY Standard.
- Single and Dual data rate capable of transmit and receive at 1.5Gb/s and 3.0 Gb/s.
- High-speed differential reference clock
- Low jitter clock synthesizers for clock distribution
- Jitter Tolerance is better than Specifications.
- 8bit/ or 10bit parallel Core logic.
- On-chip 8b/10b encoder and decoder
- High speed serial drivers
- High speed serial input stage with on-chip terminations
- On-chip Comma Detect for character alignment
- On-chip Far and Near End serial loopback test modes.
- On-chip multi pattern generator and PRBS error checker to support BIST
- Three programmable levels of pre-emphasis and equalization.
- On-chip Standard OOB sequencing with optional bypassing OOB capability.
- 1.0V ±5% Supply for logic core and control I/O.
- 1.5V HSTL / or 1.0V Parallel I/O (optional).
- Low power, 110mW max per channel.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 130nm | BCD+ | — |
Specifications
Identity
Part Number
TRC3002CSA
Vendor
TaraCom Integrated Products, Inc.
Type
Silicon IP
Files
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Provider
Learn more about Single-Protocol PHY IP core
TaraCom Introduces SerDes/PHY IPs in 90 and 65-Nanometer
TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC designs ranging from XAUI compliant, PCS/PMD functionality of the 10 Gigabit Ethernet XAUI and 10 Gigabit Fibre Channel specs as well as SATA,
Frequently asked questions about Single-Protocol PHY IP
What is Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core?
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core is a Single-Protocol PHY IP core from TaraCom Integrated Products, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.