Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

SMIC 0.18um LVDS Transceiver/Receiver

This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS.

SMIC 180nm G View all specifications

Overview

This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The LVDS transceiver is implemented in SMIC 0.18um Logic process.

Key features

  • 0.18um SMIC logic process
  • Operation frequency up to 700Mhz
  • Integrated 100 Ohm resistor in receiver
  • Do not require 1.2v reference voltage
  • Power down mode available
  • Compatible with TIA/EIA-644 LVDS standard

What’s Included?

  • Databook in electronic format
  • Verilog models and Synopsys synthesis models
  • Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II
  • LVS netlist

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G —

Specifications

Identity

Part Number
SMIC18_LVDS_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is SMIC 0.18um LVDS Transceiver/Receiver?

SMIC 0.18um LVDS Transceiver/Receiver is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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