Vendor: M31 Technology Corp. Category: Single-Protocol PHY

USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)

M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.

Contact Provider Request Datasheet
TSMC 7nm N7+ View all specifications

Overview

M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compliant with the PIPE4.0 and UTMI+ specifications. The USB 3.2 Gen2 IP integrates high-speed mixed signal circuits to support Gen2 and Gen1 traffic and is backward compatible with 480Mbps high-speed, 12Mbps full-speed, and 1.5Mbps low-speed data rates. To support USB Type-C connectors, the USB 3.2 Gen2 IP also integrates the active switch to support the bi-directional plug-in and the specific functions (USB attachment cable orientation detection and VBUS configuration) through the CC1/CC2 pins defined in Type-C connector.

Key features

  • USB 3.2 Gen2
  • 1. Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
  • 2. Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
  • 3. Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
  • 4. Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
  • Integrates an active switch to support the orientation-less connection with 5. USB Type-C connectors
  • 6. Provides an auxiliary CC module IP to support USB Type-C related functions
  • 7. Supports both Wire-bond and flip-chip package types
  • 8. Supports internal loop back and BIST functions for mass production testing
  • USB 3.2 Gen1
  • 1. Worldwide smallest USB 3.2 Gen1x1 PHY IP (e.g. IP size @28HPC+ is smaller than 0.5mm²)
  • 2. Fully compliant with Universal Serial Bus USB 3.2 Gen1x1 and 2.0 electrical specifications
  • 3. Compliant with PIPE4.0 and UTMI+ specification (Super-Speed, High-Speed, Full-Speed and Low-Speed functions)
  • 4. Supports clock inputs from 25MHz crystal oscillator or external 25MHz clock source
  • 5. Provides plenty of register controls for TX, RX, SSCG-PLL and CDR electrical parameters
  • 6. Silicon proven and mass production IP records

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ —

Specifications

Identity

Part Number
M31 USB 3.2 Gen2/Gen1 PHY IP
Vendor
M31 Technology Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact M31 Technology Corp.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)?

USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm) is a Single-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP